Field of the Invention
The invention relates to a circuit arrangement for adapting the bit rates of two signals to each other, which arrangement comprises an elastic store into which the useful data of a frame-structured first signal are written with the aid of a write address counter and read out again with the aid of a read address counter, and further comprises a phase comparator for comparing the counts of these counters.
A circuit arrangement of this type is disclosed in German Patent Application DE-A-39 20 391 (filing date: Jan. 22, 1989); in digital transmission systems this arrangement is necessary for recovering the frame-structured useful data as plesiochronous data signals. Therefore, only the useful data are written into the elastic store because the counter is stopped during all other data in the signal and the count of the write address counter denotes the addresses at which useful data are stored in the elastic store. Accordingly, the count of the read address counter denotes the addresses of the memory locations from which the useful data can be read out again.
Reading the useful data is to be effected in a manner such that the deviations from the nominal bit rate of the recovered presiochronous signal remain within the prescribed tolerance limits. A correction of the reading speed within these tolerance limits is necessary, for example, to prevent the elastic store from overflowing. Therefore, the counts of the two counters are to be monitored. The phase comparator, which produces the difference between the counts or a value equivalent thereto, is used for this monitoring. If the output signal of the phase comparator is used as a control error for a customary phase-locked loop, by means of which loop the clock for the read address counter is generated, this has the advantage that with large abrupt control errors the read clock and also the presiochronous signal will be affected by a strong jitter.
Such control errors occur, for example, when the useful data are transmitted in a Synchronous Transport Module-1 (further details below). The write address counter must then be stopped for several bytes; thus it runs highly erratically. This erratic operation is also reflected in the control error resulting in the above mentioned disadvantageous consequences for the presiochronous signal.